Research Activities

In Veri et Boni Cognitione Vera Voluptas

I remember listening to the speech given by Alberto Sangiovanni Vincentelli, now professor at Berkeley and co-founder of two very successful companies, at the opening of our 2017-2018 academic year. It spanned over teaching, research, students, startups and so on and is brilliant. Watch it and... well... be inspired. Why not? (it's in Italian)

After this, let me talk briefly about our research: in our group we have always pursued both experimental and theoretical/computational activities, in the belief that they are mutually dependent and strenghten each other. Another characteristics of our research work is that it is carried out in strong collaboration with leading companies in the field of electron devices, notably the USA semiconductor device company Micron and its Italian branch, and STMicroelectronics in Agrate and Castelletto. Collaboration with the industry allows us to access state-of-the-art technology and to work on real-life problems that affect the development of future nanoelectronic technologies, while retaining a focus on the scientific side of such problems.
Our historical activity, since about year 2000, has been on non-volatile memories, with particular emphasis on their reliability. More recently, we begun an analysis of devices and materials for galvanic isolation. Current activities are briefly detailed in the following.

Students are welcome and encouraged to join our efforts as part of their graduation or PhD thesis work. Please, refer to the thesis page for more detailed information and do not hesitate to get in touch for inquiries.

Reliability of 3D NAND Flash memories
Scaling of the conventional planar technology for non-volatile storage, based on the floating-gate MOS transistor, led all major manufacturers to reach the 14nm planar node at around 2014. However, several constraints challenged the development of the latest technolgy nodes and ultimately put a limit to the scaling of the planar technology.
To continue delivering more and more storage capacity, NAND Flash manufacturers turned to the third dimension, developing 3D integrated memory circuits, that can be roughly viewed as the result of the stacking of several 2D arrays to increase the areal storage density. Current 3D technology now delivers up to 300 stacked layers and has reached the impressive density of more than 20 Gb/mm2.
Reliability is (and has always been) a key concern for memory technologies: it is fairly easy to design a proof-of-concept memory cell that works, but is much harder to design billions of cells that work properly for a long time and after a large number of program/erase operations!
Investigation of the many physical mechanisms that play a role in such decananometer devices and end up limiting the performance or the reliability of the memory cell is our task. We strive to understand their root cause and develop appropriate models to quantify their impact on device performance, providing a feedback for technology optimization.
Examples of such issues are few-electron phenomena, threshold voltage variation due to single-electron trapping and detrapping, charge loss/gain from the storage layers.
Current conduction and fluctuation in vertical-channel devices
Both logic and memory devices are migrating toward cylindrical MOSFETs where the gate surrounds the conduction channel, as this allows for a better electrostatic control and superior performance. However, with the scaling of device dimensions comes an increased sensitivity to charge location and displacement, so that even a single-electron displacement can change appreciably the device characteristics (current, threshold voltage,...). In 3D memory devices, moreover, the conduction channel is made of polycrystalline rather than monocrystalline silicon, which complicates the underlying physics because of the presence of grain boundaries, that are highly-defective regions whose exact nature and transport properties are still under investigation.
We study the impact on the device performance of electron trapping and detrapping at the silicon/oxide interface and at the grain boundaries of modern devices. 3D Monte Carlo simulations are adopted, comparing the results against experimental data to understand the main variability sources and quantify their role.
Characterization and modeling of polymeric devices for innovative high-voltage dielectrics
In many today's applications (automotive, medical, industrial,...) there is a need to have a logic part, working at low voltage and low power, coupled to a power one, dealing with high voltage and power. The two parts must be able to exchange logic signals and data, while being electrically isolated. Traditionally, silicon oxide has been used as the isolation dielectric, but recently there is a push toward polymeric materials (polyimides) in view of some advantages in immunity to high-voltage pulses, increased thickness, and lower cost. However, such materials have been much less studied than SiO2 and their performance are yet to be assessed.
We study current transport in polymeric thin films under high voltage to establish the conduction mechanisms. Device degradation under high fields, eventually leading to breakdown, is also a main topic, whose understanding involve the comprehension of the generation of defects in the material, their evolution in time and dependence on voltage, temperaure, humidity and so on. Experimental characterization is performed in the new laboratory at Politecnico (ready in March 2023) where wafer-level as well as chip characterization can be performed.

Last modified 02/24